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| *R oH S CO M PL IA NT TISP9110LDM INTEGRATED COMPLEMENTARY BUFFERED-GATE SCRS FOR DUAL POLARITY SLIC OVERVOLTAGE PROTECTION TISP9110LDM Overvoltage Protector High Performance Protection for SLICs with +ve and -ve Battery Supplies - Wide -110 V to +110 V Programming Range - Low 5 mA max. Gate Triggering Current - Dynamic Protection Performance Specified for International Surge Waveshapes Applications include: - Wireless Local Loop - Access Equipment - Regenerated POTS - VOIP Applications Rated for International Surge Wave Shapes Wave Shape 2/10 10/700 10/1000 Standard GR-1089-CORE ITU-T K.20/21/45 GR-1089-CORE IPPSM A 100 45 30 8-SOIC (210 mil) Package (Top View) (Tip or Ring) Line (-V(BAT)) (+V(BAT)) G1 G2 1 2 3 4 8 7 6 5 NC Ground Ground NC (Ring or Tip) Line NC - No internal connection Terminal typical application names shown in parenthesis MD-8SOIC(210)-003-a Device Symbol Line ............................................... UL Recognized Component G1 G2 Description The TISP9110LDM is a programmable overvoltage protection device designed to protect modern dual polarity supply rail ringing SLICs (Subscriber Line Interface Circuits) against overvoltages on the telephone line. Overvoltages can be caused by lightning, a.c. power contact and induction. Four separate protection structures are used; two positive and two negative to provide optimum protection during Metallic (Differential) and Longitudinal (Common Mode) protection conditions in both polarities. Dynamic protection performance is specified under typical international surge waveforms from Telcordia GR-1089CORE, ITU-T K.44 and YD/T 950. Ground Line SD-TISP9-001-a The TISP9110LDM is programmed by connecting the G1 and G2 gate terminals to the negative (-V(BAT)) and positive (+V(BAT)) SLIC Battery supplies respectively. This creates a protector operating at typically +1.4 V above +V(BAT) and -1.4 V below -V(BAT) under a.c. power induction and power contact conditions. The protector gate circuitry incorporates 4 separate buffer transistors designed to provide independent control for each protection element. The gate buffer transistors minimize supply regulation issues by reducing the gate current drawn to around 5 mA, while the high voltage base emitter structures eliminate the need for expensive reverse bias protection gate diodes. The TISP9110LDM is rated for common surges contained in regulatory requirements such as ITU-T K.20, K.45, Telcordia GR-1089-CORE, YD/T 950. By the use of appropriate overcurrent protection devices such as the Bourns(R) Multifuse(R) and TelefuseTM devices, circuits can be designed to comply with modern telecom standards. How To Order Device TISP9110LDM Package 8-SOIC (210 mil) Carrier Embossed Tape Reeled Order As TISP9110LDMR-S Marking Code 9110L Standard Quantity 2000 *RoHS Directive 2002/95/EC Jan 27 2003 including Annex AUGUST 2004 - REVISED JANUARY 2007 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. TISP9110LDM Overvoltage Protector Absolute Maximum Ratings, TA = 25 C (Unless Otherwise Noted) Rating Repetitive peak off-state voltage VG1(Line) = 0, VG2 +5 V VG2(Line) = 0, VG1 -5 V Non-repetitive peak impulse current (see Notes 1, 2, 3 and 4) 2/10 s (Telcordia GR-1089-CORE) 5/310 s (ITU-T K.20, K.21 & K.45, K.44 open-circuit voltage wave shape 10/700 s) 10/1000 s (Telcordia GR-1089-CORE) Non-repetitive peak on-state current, 50 Hz / 60 Hz (see Notes 1, 2, 3 and 5) 0.2 s 1s 900 s Maximum negative battery supply voltage Maximum positive battery supply voltage Maximum differential battery supply voltage Junction temperature Storage temperature range ITSM VG1M VG2M V(BAT)M TJ Tstg 9.0 5.0 1.7 -110 +110 220 -40 to +150 -65 to +150 A V V V C C IPPSM 100 45 30 A Symbol VDRM Value -120 +120 Unit V NOTES: 1. Initially the device must be in thermal equilibrium with TJ = 25 C. The surge may be repeated after the device returns to its initial conditions. 2. The rated current values may be applied to either of the Line to Ground terminal pairs. Additionally both terminal pairs may have , their rated current values applied simultaneously (in this case the Ground terminal current will be twice the rated current value of a single terminal pair). 3. Rated currents only apply if pins 6 & 7 (Ground) are connected together. 4. Applies for the following bias conditions: VG1 = -20 V to -110 V, VG2 = 0 V to +110 V. 5. EIA/JESD51-2 environment and EIA/JESD51-7 high effective thermal conductivity test board (m ulti-layer) connected with 0.6 mm printed wiring track widths. Electrical Characteristics for any Section, TA = 25 C (Unless Otherwise Noted) Parameter ID IG1(Line) IG2(Line) VG1L(BO) VG2L(BO) IHIG1T IG2T CO NOTE: Off-state current VD = VDRM, VG2(Line) = 0, VG1 -5 V Negative-gate leakage current Positive-gate leakage current Gate - Line impulse breakover voltage Gate - Line impulse breakover voltage Negative holding current Negative-gate trigger current Positive-gate trigger current Line - Ground off-state capacitance VG1(Line) = -220 V VG2(Line) = +220 V VG1 = -100 V, IT = -100 A (see Note 6) VG1 = -100 V, IT = -30 A VG2 = +100 V, IT = +100 A (see Note 6) VG2 = +100 V, IT = +30 A VG1 = -60 V, IT = -1 A, di/dt = 1 A/ms IT = -5 A, tp(g) 20 s, VG1 = -60 V IT = 5 A, tp(g) 20 s, VG2 = 60 V f = 1 MHz, VD = -3 V, G1 & G2 open circuit 32 2/10 s 10/1000 s 2/10 s 10/1000 s -150 +5 -5 Test Conditions VD = VDRM, VG1(Line) = 0, VG2 +5 V TA = 25 C TA = 85 C TA = 25 C TA = 85 C Min Typ Max Unit -5 -50 +5 +50 -5 +5 -15 -11 +15 +11 A A A V V mA mA mA pF 6. Voltage measurements should be made with an oscilloscope with limited bandwidth (20 MHz) to avoid high frequency noise. AUGUST 2004 - REVISED JANUARY 2007 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. TISP9110LDM Overvoltage Protector Thermal Characteristics, TA = 25 C (Unless Otherwise Noted) Parameter RJA NOTE Junction to ambient thermal resistance Test Conditions EIA/JESD51-7 PCB, EIA/JESD51-2 Environment, PTOT = 4 W (See Note 7) Min Typ Max 55 Unit C/W 7. EIA/JESD51-7 high effective thermal conductivity test board (multi-layer) connected with 0.6 mm printed wiring track widths. Parameter Measurement Information +i IPPSM ITSM ITRM V(BO) Quadrant I Switching Characteristic IH -v V G1 VD ID ID VD V G2 +v IH V(BO) ITRM Quadrant III Switching Characteristic -i ITSM IPPSM PM-TISP9-001-a Figure 1. Voltage-Current Characteristic Unless Otherwise Noted, All Voltages are Referenced to the Ground Terminal AUGUST 2004 - REVISED JANUARY 2007 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. TISP9110LDM Overvoltage Protector Typical Characteristics Thermal Information ITSM(t) - Non-Repetitive Peak On-State Current - A 50 45 Co - Off-state Capacitance - pF 40 35 30 25 20 15 10 0.1 OFF-STATE CAPACITANCE vs OFF-STATE VOLTAG E TC-TISP9-001-a NON-REPETITIVE PEAK ON-STATE CURRENT vs CURRENT DURATION 15 10 9 8 7 6 5 4 3 2 1.5 1 0.1 TI-TISP9-001-a V GEN = 600 Vrms, 50/60 Hz RGEN = 1.4*V GEN/ITSM(t) EIA/JESD51-2 ENVIRONMENT EIA/JESD51-7 PCB, TA = 25 C SIMULTANEOUS OPERATION OF R AND T TERMINALS. GROUND TERMINAL CURRENT = 2 x ITSM(t) TJ = 25 C V d = 1 Vrms 1 10 V D - Off-state Voltage - V 100 1 10 100 1000 t - Current Duration - s Figure 2. Figure 3. AUGUST 2004 - REVISED JANUARY 2007 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. TISP9110LDM Overvoltage Protector APPLICATIONS INFORMATION Overcurrent Protection Tip SLIC SLIC PROTECTOR C1 220 nF C2 220 nF Ring TISP9110LDM +V BAT D1 -VBAT Figure 4. Typical Application Diagram GR-1089-Core Intra Building Overcurrent Protection 1 GR-1089-CORE Overcurrent Protection 2 ITU-T K20 (Basic) Overcurrent Protection 3 ITU-T K20 (Enhanced) Overcurrent Protection 4 F1a B0500T + t MF-SM013-250 Telcordia GR-1089-CORE Issue 3 compliant LFR (Custom) + t 35 CPTC * 2027-35 GDT (Bourns) F1b B0500T + t MF-SM013-250 + t 35 CPTC * Agreed Primary AI-TISP9-001-a Figure 5. Typical Overcurrent Protection "TISP" is a trademark of Bourns, Ltd., a Bourns Company, and is Registered in U.S. Patent and Trademark Office. "Bourns" is a registered trademark of Bourns, Inc. in the U.S. and other countries. AUGUST 2004 - REVISED JANUARY 2007 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. |
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